Wafer Level AlGe Eutectic Bonding for MEMS-Electronic-Photonic Heterogeneous Integration

An AlGe eutectic wafer level bonding process is presented and characterized for heterogeneous integration of silicon photonics, CMOS integrated electronic circuits and active III-V components. Heterogeneous Integration of Photonics and CMOS The technology of silicon photonics integrated circuits (SiPIC) currently finds itself transitioning from research to industrial scale production [1]. The promises of the technology are manifold, including high bandwidth, high circuit density, low power consumption, etc. [2]. At the integrated photonics laboratory at UC Berkeley, we are developing a modular approach for fabrication of heterogeneously integrated, combined electronic and photonic circuits. In this paper, we discuss the recent developments of an aluminum-germanium eutectic bonding process that allows wafer level integration of silicon photonics and CMOS electronic integrated circuits. An example of a heterogeneously integrated optoelectronic circuit is illustrated in Fig. 1: integrating MEMS tunable lasers, silicon photonics and CMOS circuits for frequency control would allow fabrication of a source chip for frequency-modulated continuous-wave laser detection and ranging applications. Such integrated optoelectronic integrated circuits are expected to enable revolutionary applications, such as 3D-imaging in mobile applications and for autonomous vehicles, 3D cartography, gesture based computing, etc. Fig. 1: Schematic representation of a heterogeneously integrated optoelectronic circuit, featuring active III-V, passive silicon photonics and integrated electronics. This paper reports on a wafer level integration process of the silicon photonics and the electronics wafers (the two lower levels in the figure). Fig. 2: Fabrication process of the test structures: a) oxide deposition, AlGe deposit and etch, backside alignment mark etch, b) wafer level bonding, c) dicing, and d) substrate removal. The upper wafer simulates a silicon photonics wafer, the lower a CMOS integrated electronics wafer. AlGe Eutectic Wafer Bonding Eutectic bonding is a wafer level bonding technology, that uses an intermediate metal layer between the two bonding interfaces. With a eutectic alloy composition, the melting point of the alloy can be drastically reduced compared to the pure metals. For the AlGe system, the thickness ratio of 0.59tAluminum = tGermanium corresponds to the eutectic composition, which exhibits a melting point of 424°C [3]. In the integration scheme for heterogeneous integration of photonic and electronic integrated circuits, the metal-metal bonding allows for thermal and electrical via from the silicon photonics layer to the electronics layer. Experimental Procedure In order to develop an Al-Ge bonding process for heterogeneous integration of silicon photonics and CMOS wafers, substrates mimicking the silicon photonics wafer and the CMOS wafer have been fabricated. The fabrication process of these substrates is depicted in Fig. 2: A low temperature oxide (LTO) (2um) is deposited on 4” double side polished silicon wafers. The 2um thick oxide layer is representative for silicon photonics layer on a silicon on insulator (SOI) platform, and at the same time, can be used as a model for passivation of an integrated electronic circuit. This allows to develop a suitable integration process without the need of expensive CMOS and SiPIC wafers. 500nm aluminum and 295nm germanium layers are deposited in the same process step using e-beam evaporation. The metallized wafers are patterned using standard lithography and wet etching technology. The test patterns included square bond pads of different sizes. Backside alignment marks are etched into the backside oxide layer for subsequent alignment of the wafers using an EVG620 aligner; the aligned wafers are bonded in an EVG501 wafer bonder, following a bonding recipe with 450°C bonding temperature during 30min, at 1-3kN tool pressure and 10 -2 mbar chamber pressure [3]. Substrate removal was achieved using a SF6 isotropic dry etch process. Results and Discussion Aligned bonding has been achieved with alignment accuracy better than 3um (Fig. 3a). The bonded wafers exhibited bond strength of 8 J/m 2 (measured on unpatterned wafers using Maszara’s [4] crack opening method). This bond strength allows the subsequent process steps of dicing and substrate removal. Fig. 3b shows an oxide surface after substrate removal. The interference fringes indicate substantial bending of the oxide membrane due to compressive stress, and the microstructure in the AlGe alloy confirms the melting of the eutectic alloy, leading to a strong bond. Profilometer measurements show the amount of bending of the membrane with respect to the membrane length (Figure 3c). For a membrane length of 40um, the bending of the 2um LTO membrane remains below 100nm. Fig. 3a: IR transmission micrograph of 10um square patterns (20um pitch) on bonded wafers. The insets shows the misalignment <3um. Fig. 3b: Micrograph of 70um square AlGe bond patterns, seen through the oxide membrane; Interference fringes indicate bending of the oxide membrane. Fig. 3c: Maximum height of the oxide membrane measured by profilometry. The 2um LTO membrane bends less than 100nm up to a gap size of 40um. Conclusions and Outlook An AlGe eutectic bonding process has successfully been applied to substrates simulating silicon photonics and CMOS electronics wafers. Alignment better than 3um was achieved and bond strength of 8 J/m 2 is reported. 2um LTO membranes below 40um width show bending less than 100nm due to compressive stress, while in membranes with a width >70um, stress exceeds the rupture strength of silicon oxide and the membranes crack. These findings provide experimental data for design guidelines of a wafer level AlGe eutectic bonding process for heterogeneous integration of silicon photonics and CMOS integrated electronic circuits.